FIG. 1 is a schematic diagram of a prior art RMS-DC converter system. The system of FIG. 1 includes an RMS-DC converter subsystem 10, a variable gain amplifier (VGA) 12, and an operational amplifier (op amp) 14.
The subsystem 10 performs an implicit RMS computation and includes an absolute value/voltage-current converter 16, a one-quadrant squarer/divider 18, and a current mirror 20. The input voltage V1, which can be either AC or DC, is converted to a unipolar current I1 by an active rectifier formed by op amps A1 and A2. The current I1 drives the input of the squarer/divider. The output current I4 of the squarer/divider drives the current mirror through a low-pass filter formed by resistor R1 and capacitor CAV. If the R1,CAV time constant is much greater than the longest period of the input signal, then I4 is effectively averaged.
The current mirror returns a current I3, which equals the average of I4, back to the squarer/divider to complete the implicit RMS computation. The current mirror also produces the output current IOUT, which can be used directly or converted to a voltage with RL. An optional dB output can be derived from the emitter of Q3 since the voltage at this point is proportional to -log V1. Emitter follower transistor Q5 buffers and level shifts this voltage so that the dB output voltage is zero when the externally supplied emitter current IREF to Q5 approximates I3.
The RMS subsystem 10 of FIG. 1 can operate independently as a complete RMS-DC converter. However, it suffers from numerous problems such as limited dynamic range, and bandwidth that depends on the signal level. To overcome these problems, the system of FIG. 1 utilizes the RMS subsystem as merely the detector element in an automatic gain control (AGC) loop in which the difference between the RMS output of the subsystem 10 and a fixed DC reference are nulled in a loop integrator. The loop integrator includes an op amp 16 and a variable gain amplifier (VGA) 12. The op amp generates the output voltage VOUT in response to the output voltage VRMS from the RMS subsystem and the reference voltage VREF. Resistors R6 and R7 divide VOUT to generate the gain control signal VG, which controls the gain of the VGA. The dynamic range and accuracy with which the signal can be determined are now entirely dependent on the VGA. Since the input to the RMS subsystem is forced to a constant amplitude, close to its maximum input capability, the bandwidth is no longer signal dependent.
Although the system of FIG. 1 can perform wide dynamic range RMS-DC measurements, it suffers from other limitations. For example, the circuitry in the RMS subsystem limits the maximum frequency at which the system can operate. There is also some redundancy, inasmuch as there is no need to compute the full root mean-square value.
In one aspect of the present invention, an RMS-DC converter utilizes a variable gain amplifier to drive a squaring cell. In another aspect of the present invention, an RMS-DC converter drives a first squaring cell with a variable gain amplifier and drives a second squaring cell with a reference signal. In a further aspect of the present invention, an RMS-DC converter drives a first detector with a signal to be measured, and a second detector with a replica signal. In another aspect of the present invention, a variable gain amplifier is utilized to amplify either the signal to be measured or the replica signal.
In an additional aspect of the present invention, an input system for a continuously interpolated amplifier includes gm stages wherein the current from one of the transistors in each gm stage is diverted to an AC ground through a feedforward path.